1. Field of the Invention
The present invention relates to semiconductor devices and methods of controlling a data strobe thereof, and more particularly to semiconductor memory devices having an interface of an open drain type or a pseudo-open drain type and methods of controlling a data strobe thereof.
2. Description of the Related Art
In a more advanced memory system than a double data rate (DDR) memory system, a data strobe signal (hereinafter referred to as a data strobe signal DQS) is typically used for an input/output of data. When a READ command is executed in a dynamic random access memory (DRAM), data synchronized to the data strobe signal DQS are outputted. The data strobe signal DQS has a preamble section and a postamble section. In a data output section, the data strobe signal DQS toggles between a logic level ‘L’ and a logic level ‘H’.
FIG. 1 is a timing diagram illustrating a preamble section and a postamble section of a data strobe signal DQS in a common DDR3 memory.
Referring to FIG. 1, when a column address is activated according to a READ command, data is read after a predetermined column address strobe (CAS) latency (CL, for example CL=8). The data strobe signal DQS remains in a high-impedance level Hi-Z during a normal period. The data strobe signal DQS, however, has a preamble section (section A in FIG. 1) which maintains a low level by one clock in advance before reading data. After the preamble section, the data strobe signal DQS toggles according to a data read timing. The data strobe signal DQS has a postamble section (section B in FIG. 1) after a data read section, and then returns back to the high impedance level Hi-Z.
In the case of a semiconductor device having an input/output interface of an open drain type or a pseudo-open drain type, for example, a DDR3 memory, the high impedance level Hi-Z of the data strobe signal DQS corresponds to a high level H.
In the postamble section of the data strobe signal DQS with which the READ operation is finished, the data DQ and the data strobe signal DQS maintain the high impedance level Hi-Z and attain a level VDDQ by a termination voltage.
States of a DQS pin in a postamble section and a subsequent section next to the postamble section are shown in Table 1.
TABLE 1High Section of Next CLKLow Section of CLK(Following Section Next to(Postamble Section)Postamble Section)DQS Output StateLHi-ZDQS Pin LevelLVDDQ
FIG. 2 is a graph illustrating a ringing effect of a DQS pin voltage. A DQS input impedance has a nearly infinite value, and a total reflection occurs. A reflected wave due to the above impedance mismatch causes the ringing effect or ripples of the DQS pin voltage as shown in FIG. 2.
FIG. 3 is a block diagram illustrating a DQS output circuit of a conventional memory device, and FIG. 4 is a block diagram illustrating a DQS control signal generating circuit of a conventional memory device. FIG. 5 is a timing diagram illustrating a preamble section and a postamble section of a DQS output circuit of a conventional memory device.
Circuits similar to that illustrated in FIG. 3 are used for outputting a data strobe signal DQS according to a proper timing. The signals PTRSTDS_F and PTRSTDS_S are DQS control signals for toggling the data strobe signal DQS in the READ operation of the memory device. The signal PTRSTDS_S may be delayed by a ½ clock with respect to the signal PTRSTDS_F.
The DQS output circuit includes a first control circuit 310, a second control circuit 320, a p-channel metal oxide semiconductor (PMOS) transistor PT1 and an n-channel metal oxide semiconductor (NMOS) transistor NT1 as shown in FIG. 3.
Referring to FIGS. 3 and 5, the first control circuit 310 turns on the PMOS transistor PT1 and causes a DQS pin (PAD) to be in a high state H when both the signal PTRSTDS_F and a clock signal CLK are in a high state in sections P12 and P14. The first control circuit 310 may be realized by using the signal PTRSTDS_F and the signal CLK as inputs of an AND gate. In addition, the first control circuit 310 may be realized so that the signal PTRSTDS_F may be prefetched during a low (‘L’) section of the clock signal CLK and may be outputted during a high (‘H’) section of the clock signal CLK.
The second control circuit 320 turns on the NMOS transistor PT1 and causes the DQS pin (PAD) to be in a low state when the signal PTRSTDS_F is in a high state and a clock signal CLK is in a low state in sections P13 and P15.
When both the first control circuit 310 and the second control circuit 320 do not operate, both the NMOS transistor NT1 and the PMOS transistor PT1 are turned off. As a result, the state of the DQS pin becomes the high impedance state Hi-Z in sections P11 and P16.
Referring to FIG. 4, a DQS control signal LATENCYDS that controls a timing point of outputting READ data based on the CL is fetched according to a clock signal CLK. The signal LATENCYDS passes through delay circuits 407 and 409 to generate the signals PTRSTDS_S and PTRSTDS_F.
When the ringing effect occurs as shown in FIG. 2, a problem of accepting invalid data occurs in the semiconductor memory device, which accesses the data by counting a number of DQS togglings. In addition, the ringing effect itself may increase a noise level of a controller board, and may cause a limitation to an operation speed, and more particularly in a high frequency operation.